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[DSP program2812RAM

Description: TMS320F2812读写外部RAM的C语言例程,TMS320F2812读写外部RAM的C语言例程-TMS320F2812 external RAM read and write the C language routines, TMS320F2812 external RAM read and write the C language routines
Platform: | Size: 36864 | Author: 王磊 | Hits:

[VHDL-FPGA-Verilogvga_hex_disp

Description: 该项目可在VGA显示器上显示RAM或ROM中的十六进制数据,使用VerilogHDL语言编写,在QuartusII开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Platform: | Size: 18432 | Author: submars | Hits:

[Program docDual_port_RAM

Description: 很精彩的双端口RAM应用笔记,对搞单片机、FPGA的都有帮助。-dual_port_ram
Platform: | Size: 644096 | Author: chenlei | Hits:

[SCMFIFO

Description: FIFO中文应用笔记,对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
Platform: | Size: 1136640 | Author: chenlei | Hits:

[VHDL-FPGA-Verilogprofiles

Description: source code of counter,ram,lfsr etc
Platform: | Size: 2048 | Author: narsimha | Hits:

[Software EngineeringTopLevel_DualPort_Ram_XilinxCore

Description: Top Level Dual Port Ram Core Project, VHDL code
Platform: | Size: 1024 | Author: mohd | Hits:

[VHDL-FPGA-Verilogconnect20090223

Description: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Platform: | Size: 468992 | Author: 张菁 | Hits:

[VHDL-FPGA-VerilogXAPP204

Description: Using Block RAM for High-Performance Read.Write Cams
Platform: | Size: 55296 | Author: ryan | Hits:

[Software EngineeringUSB2RAM

Description: Module usb ram - bardzo uzyteczny do komunikacji z innymi urzadzeniami-Module usb ram- bardzo uzyteczny do komunikacji z innymi urzadzeniami
Platform: | Size: 1585152 | Author: student | Hits:

[VHDL-FPGA-Verilogfpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷(GRAY)变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点,使得整个系统可靠性高和抗干扰能力强,系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构,使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[VHDL-FPGA-VerilogDW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[OS Developprogram

Description: 设计实现4bit FIFO, 数据深度为8, 产生满, 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Platform: | Size: 3072 | Author: shao | Hits:

[VHDL-FPGA-VerilogFPGA_Design_Guide_Chapter1_Westor

Description:
Platform: | Size: 2136064 | Author: 陈枫 | Hits:

[Communicationcontrol

Description: Turbo码编码器时序控制模块,能够对于RAM,ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
Platform: | Size: 1024 | Author: sunhao | Hits:

[Otherinterleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-VerilogZBTSRAM

Description: 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
Platform: | Size: 8192 | Author: wang | Hits:

[VHDL-FPGA-VerilogRAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[VHDL-FPGA-Verilogdpram2

Description: vhdl写的双口ram,真正实现双口通信-I write vhdl dual ram, true dual-port communication
Platform: | Size: 2832384 | Author: fenglei | Hits:

[VHDL-FPGA-Veriloglpm_ram

Description: 一个基于quartus的LPM_RAM例子,VHDL语言写的,通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
Platform: | Size: 221184 | Author: a64577122 | Hits:

[VHDL-FPGA-VerilogSouceCode_0f_DDR_SDRAM_Controller_by_VHDL

Description: VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
Platform: | Size: 683008 | Author: SYQ | Hits:
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